1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device having a multi-layer structure.
2. Description of the Related Art
In a technical field of semiconductor devices, higher performance and lower electric power consumption have been promoted by miniaturization and higher integration. In order to increase the integration of semiconductor integrated circuits, a multi-layer integrated circuits with integrated circuits (semiconductor element layer) of a multi-layer structure have been proposed.
As an example of manufacturing such a multi-layer integrated circuit, a method in which an interlayer insulator of an organic material is formed over a first semiconductor element layer which is formed over a substrate, and a second semiconductor element layer is stacked over the interlayer insulator has been disclosed (for example, see Patent Document 1: Japanese Published Patent Application No. H5-335482).
In addition, as another example of manufacturing such a multi-layer integrated circuit, a method in which a first semiconductor element layer and a second semiconductor element layer formed over different substrates are bonded with an epoxy resin so as to be in contact with each other to have a multi-layer structure has been disclosed (for example, see Patent Document 2: Japanese Published Patent Application No. 2001-189419).    [Patent Document 1] Japanese Published Patent Application No. H5-335482    [Patent Document 2] Japanese Published Patent Application No. 2001-189419